View LTC4224IMS-1-PBF_4344694.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LTC4224-1/LTC4224-2 Compact Dual Low Voltage Hot Swap Controller FEATURES
n n n n n n n n n n n
DESCRIPTION
The LTC(R)4224 Dual Low Voltage Hot SwapTM controller allows a board to be safely inserted and removed from a live backplane. It controls two supplies with external Nchannel MOSFETs and operates with one supply as low as 1V provided the other supply is 2.7V or greater. The LTC4224 can ramp up the supplies in any order and at adjustable ramp rates. To minimize the number of external components and PCB area, the gate capacitor is optional, all timing delays are generated internally, and the ON pins have integrated pull-up currents. Protection against overcurrent faults is provided by a fastacting current limit and timed circuit breakers. A FAULT pin signals overcurrent faults. The LTC4224-1 remains off after a fault, while the LTC4224-2 automatically tries to apply power again after a four second cool-down period.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Allows Safe Board Insertion and Removal from a Live Backplane Controls Load Voltages from 1V to 6V No Gate Components Required Adjustable Current Limit with Circuit Breaker Limits Peak Fault Current in 1s No External Timing Capacitor Required Adjustable Supply Voltage Power-Up Rate Gate Drive for External N-channel MOSFET LTC4224-1: Latchoff After Fault LTC4224-2: Automatic Retry After Fault 10-Lead MSOP and 3mm x 2mm DFN Packages
APPLICATIONS
n n n
Optical Networking Low Voltage Hot Swap Electronic Circuit Breakers
TYPICAL APPLICATION
0.015 5V 0.010 3.3V FDS6911 5V 1A 3.3V 2A VOUT1 5V/DIV VOUT2 5V/DIV
Normal Power-Up Waveform
VCC1 SENSE1 VCC2
SENSE2 GATE1 GATE2
LTC4224 LTC4224 FAULT
ON1 ON2 GND GND
IIN1 2A/DIV
IIN2 2A/DIV CLOAD = 150F 0.5ms/DIV
422412 TA01b
CONNECTOR PLUG-IN CARD
422412 TA01a
422412fa
1
LTC4224-1/LTC4224-2 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VCCn) .................................. -0.3V to 9V Input Voltages SENSEn, ONn........................................... -0.3V to 9V Output Voltages GATEn - VCC (Note 4) .............................. -0.3V to 5V FAULT....................................................... -0.3V to 9V
Operating Temperature Range LTC4224C ................................................ 0C to 70C LTC4224I.............................................. -40C to 85C Storage Temperature Range .................. -65C to 150C Lead Temperature Range (Soldering, 10 sec) MSOP Package ................................................. 300C
PIN CONFIGURATION
TOP VIEW SENSE1 1 VCC1 2 GATE1 3 FAULT 4 ON1 5 11 10 SENSE2 9 VCC2 8 GATE2 7 GND 6 ON2 SENSE1 VCC1 GATE1 FAULT ON1 1 2 3 4 5 TOP VIEW 10 9 8 7 6 SENSE2 VCC2 GATE2 GND ON2
DDB PACKAGE 10-LEAD (3mm x 2mm) PLASTIC DFN TJMAX = 125C, JA = 43C/W EXPOSED PAD (PIN 11) PCB GND CONNECTION OPTIONAL
MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125C, JA = 160C/W
ORDER INFORMATION
LEAD FREE FINISH LTC4224CDDB-1#PBF LTC4224CDDB-2#PBF LTC4224IDDB-1#PBF LTC4224IDDB-2#PBF LTC4224CMS-1#PBF LTC4224CMS-2#PBF LTC4224IMS-1#PBF LTC4224IMS-2#PBF TAPE AND REEL LTC4224CDDB-1#TRPBF LTC4224CDDB-2#TRPBF LTC4224IDDB-1#TRPBF LTC4224IDDB-2#TRPBF LTC4224CMS-1#TRPBF LTC4224CMS-2#TRPBF LTC4224IMS-1#TRPBF LTC4224IMS-2#TRPBF PART MARKING* LDTT LDNV LDTT LDNV LTDTV LTDNW LTDTV LTDNW PACKAGE DESCRIPTION 10-Lead (3mm x 2mm) Plastic DFN 10-Lead (3mm x 2mm) Plastic DFN 10-Lead (3mm x 2mm) Plastic DFN 10-Lead (3mm x 2mm) Plastic DFN 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP TEMPERATURE RANGE 0C to 70C 0C to 70C -40C to 85C -40C to 85C 0C to 70C 0C to 70C -40C to 85C -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
422412fa
2
LTC4224-1/LTC4224-2 ELECTRICAL CHARACTERISTICS
SYMBOL Supplies VCC ICC VCC(UVL) VCCLO ICCLO VCCLO(UVL) External Gate Drive VGATE IGATE(UP) IGATE(DN) IGATE(FPD) Current Limit VSENSE(CB) ISENSE Inputs and Outputs VON(TH) VON(HYST) ION(IN) VOL Delay tCB tPHL(SENSE) tPLH(GATE) tPLH(UVL) tD(UV) tD(COOL) tBLANK Circuit Breaker Delay Sense Voltage, (VCCn - SENSEn) High to GATE Low ONn Low or Input Supply High to GATEn High Prop Delay VCCn Low to GATEn Low Prop Delay UV Turn-On Delay Auto-Retry Cooling Delay Start-Up Circuit Breaker Blanking Delay VCC Out of UV Note 3 VSENSE = 200mV, CGATE = 10nF
l l l l l l l
The l denotes the specifications which apply over the full operating temperature range. TA = 25C, VCC1 = 5V, VCC2 = 3.3V, unless otherwise noted.
PARAMETER VCC Supply Range VCC Supply Current VCC Undervoltage Lockout VCCLO Supply Range VCCLO Supply Current VCCLO Undervoltage Lockout Gate Drive (VGATEn - VCC) Gate Pull-Up Current Gate Pull-Down Current Gate Fast Pull-Down Current Circuit Breaker Trip Sense Voltage (VCCn - SENSEn) SENSE Input Current ONn Threshold Voltage ONn Hysteresis ONn Pull-Up Current Output Low Voltage (FAULT) VONn = 1V IFAULT = 3mA VSENSE1 = 5V, VSENSE2 = 3.3V VONn Rising VCCLO Falling IGATEn = 0A, -1A Gate Drive On, VGATEn = 1V VONn = 1V, VGATEn = 10V Fast Turn-Off, VGATEn = 10V VCC Rising VCCLO = Min (VCC1, VCC2), VCC 2.7V CONDITIONS VCC = Max (VCC1, VCC2)
l l l l l l l l l l l l l l l l
MIN 2.7
TYP
MAX 6
UNITS V mA V V A V V A mA mA mV A V mV A V ms s ms s ms s ms
1.4 2.2 1 40 0.76 4.5 -7 0.5 50 22.5 0.8 5.5 -10 1.5 125 25 40 0.76 15 -5 0.8 30 -10 0.2 2.5 5 0.4 5 10 8 80 2 2.5 160 4 5 2.4
3 2.65 6 100 0.84 7 -13 3 200 27.5 100 0.84 50 -15 0.4 7.5 1 15 16 240 6 7.5
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to GND unless otherwise specified.
Note 3: LTC4224-2 only. Note 4: The greater of VCC1 and VCC2 is the internal supply voltage (VCC). An internal clamp limits the GATE pin to a minimum 5V above VCC. Driving this pin beyond the clamp may damage the device.
422412fa
3
LTC4224-1/LTC4224-2 TYPICAL PERFORMANCE CHARACTERISTICS
Specifications are TA = 25C, VCC1 = 5V, VCC2 = 3.3V, unless otherwise specified. ICC vs VCC
1.5 26.0 25.5 25.0 VCB (mV) ICC (mA) 24.5 24.0 1.1 23.5 23.0 5.1 tCB (ms) 1 2 3 VCC (V)
422412 G01 422412 G02
Circuit Breaker Trip Voltage vs VCC
5.5
Circuit Breaker Delay vs VCC
1.4
5.4
1.3
5.3
1.2
5.2
1.0 2.5
3
3.5
4.5 4 VCC (V)
5
5.5
6
4
5
6
5.0 2.5
3
3.5
4 4.5 VCC (V)
5
5.5
6
422412 G03
Gate Drive vs IGATE
6 5 4 VGATE (V) VGATE (V) 3 2 1 0 5.65 5.60 5.55 5.50 5.45 5.40
Gate Drive vs Temperature
GATE NORMAL PULL-DOWN CURRENT (mA) 2.0
Gate Pull-Down Current vs Gate Voltage
1.8
1.6
1.4
1.2
0
-2
-4
-6 -8 IGATE (A)
-10
-12
422412 G04
5.35 -50
1.0 -25 0 25 50 TEMPERATURE (C) 75 100
422412 G05
8
9
10 11 VGATE (V)
12
13
422412 G06
Gate Fast Pull-Down Current vs Gate Voltage
150 GATE FAST PULL-DOWN CURRENT (mA) ACTIVE CURRENT LIMIT DELAY (s) 1.5
Active Current Limit Delay vs Sense Voltage
500
FAULT Voltage vs FAULT Sink Current
140
1.2
400 T = 90C VOL (mV)
130
0.9
300 T = 25C 200 T = -60C
120
0.6
110
0.3
100
100
8
9
10 11 VGATE (V)
12
13
422412 G07
0.0
25
50
75 100 125 SENSE VOLTAGE (mV)
150
422412 G08
0
0
1
2 3 IFAULT (mA)
4
5
422412 G09
422412fa
4
LTC4224-1/LTC4224-2 PIN FUNCTIONS
SENSE1, SENSE2 (Pins 1,10): Current Sense Input. Connect this pin to an external sense resistor. The current limit circuit controls GATEn to limit the voltage between VCCn and SENSEn to 25mV. An Electronic Circuit Breaker (ECB) is active during current limiting and trips after 5ms. To disable current limit, connect this pin to VCCn. VCC1, VCC2 (Pins 2, 9): Supply Voltage and Current Sense Input. An undervoltage lockout circuit disables the part until VCC , the higher of VCC1 and VCC2, exceeds 2.4V. The lower supply is disabled until it exceeds 0.8V. GATE1, GATE2 (Pins 3, 8): Gate Drive for External N-channel MOSFET. A charge pump sources 10A from GATE to turn on the external MOSFET. An internal clamp limits the gate voltage to 5.5V above the higher of VCC1 and VCC2. During turn-off, a 1.5mA pulldown current discharges GATE to ground. During short-circuits, a 125mA pulldown current is activated to discharge GATE to ground. FAULT (Pin 4): Fault Status Output. Open-drain output that is normally pulled high to VCC1 or VCC2 by an external resistor. It is pulled low when the ECB trips due to an overcurrent condition at either supply. This pin may be left open if unused. ON1, ON2 (Pins 5, 6): On Control Input. A falling edge turns on the external N-channel MOSFET and a rising edge turns it off. A low to high transition on this pin resets an ECB fault for the corresponding channel. Internally pulled up to VCC by a 10A current source. GND (Pin 7): Device Ground. Exposed Pad (DFN Package Only): Exposed Pad may be left open or connected to device ground.
FUNCTIONAL DIAGRAM
SENSE1 CHARGE PUMP 10A ACL1 GATE1 VCC GATE PULLDOWN 10A ON1 5.5V VCC
+
ECB1 0.8V VCC ON1
-
VCC1 UV
+
2.4V
-
+
0.8V VCC2 25mV
- + -
SENSE2 ACL2
+ -
+
LOGIC CONTROL VCC2 UV ECB2 CHARGE PUMP 10A VCC GND
VCC1
25mV
+ -
-
+ -
0.8V
FAULT VCC 10A ON2
ON2
+ -
0.8V
GATE PULLDOWN 5.5V
GATE2
422412 FD
422412fa
5
LTC4224-1/LTC4224-2 OPERATION
The LTC4224 is designed to control power on a live backplane, allowing boards to be safely inserted and removed. It controls two supplies (VCC1, VCC2) with operating voltages between 1V and 6V via two external N-channel MOSFETs. For applications where the total load current is 5A or less, dual MOSFETs such as the FDS6911 can be used to save board area. The two supplies can be turned on and off independently using the active low ON1 and ON2 pins. Internal 10A current sources pull these pins to VCC. Pulling the ON pin low turns on a charge pump which sources 10A at the GATE pin thereby ramping up the gate of the external MOSFET. When the MOSFET turns on, the inrush current is limited at a level set by an external sense resistor. Inrush current can be further reduced, if desired, by adding a capacitor from GATE to GND. To protect the external MOSFET, the GATE pins are clamped to about 5.5V above the higher of the two supplies. Each supply is continuously monitored for undervoltage and overcurrent conditions. The undervoltage monitor shuts off the external MOSFET when the corresponding supply is too low. Current is monitored by an active current limit amplifier (ACL) and a timed electronic circuit breaker (ECB). Like all timing delays in the LTC4224, the ECB delay of 5ms is generated internally without requiring any external timing capacitors. The ECB threshold is slightly below the ACL threshold and shuts off the external MOSFET after 5ms. FAULT is latched low to indicate an overcurrent fault. The LTC4224-1 remains latched off until reset by either turning off and then on the affected supply or its ON pin. The LTC4224-2 automatically restarts after four seconds to allow time for the MOSFET to cool down.
APPLICATIONS INFORMATION
The typical LTC4224 application is in a high availability system where two positive supply voltages are distributed to power individual cards. The LTC4224 detects board presence during insertion and removal, allowing power to be delivered in a controlled manner without damaging the connector. It reports overcurrent faults to the system controller through its FAULT pin, which can light an LED or can be monitored by a system controller.
R1 0.015 5V BULK SUPPLY BYPASS CAPACITOR 3.3V BULK SUPPLY BYPASS CAPACITOR Q2 R3 390 VCC1 SENSE1 VCC2 SENSE2 GATE1 GATE2 ON1 LTC4224 FAULT ON2 GND MOD DETECT RMOD_DET 1k GND Q1 R2 0.010
The basic LTC4224 application circuit is shown in Figure 1. The following sections cover VCC selection, the normal turn-on and turn-off sequence, various fault conditions and recovery from fault situations. External component selection is discussed in detail in the Design Example section.
FDS6911 5V 1A
3.3V 2A
D1
CONNECTOR
PLUG-IN CARD
Figure 1. Typical Application
422412fa
6
LTC4224-1/LTC4224-2 APPLICATIONS INFORMATION
VCC Selection The LTC4224 is powered from the higher of its two supply pins, VCC1 and VCC2.This allows the part to control a supply voltage as low as 1V, while the other supply is 2.7V or greater. If both supplies are tied together, the part derives its power from both equally. The Functional Diagram shows the VCC selection circuit in an ideal diode OR-ing arrangement. It is designed to ensure swift and smooth internal power switchover from one supply to the other. Turn-On Sequence Separate ON1 and ON2 pins allow the VCC1 and VCC2 supplies to be turned on in any order. The power supplies delivered to a plug-in card are controlled by external Nchannel MOSFETs, Q1 and Q2. For X2/XENPAK defined optical transceiver modules, it has been specified that the MOD DETECT pin pulls low inside the module through a 1k resistor (RMOD_DET), as shown in Figure 1. Several conditions must be satisfied to turn on the MOSFETs. First, VCC1 or VCC2 must exceed the 2.4V VCC undervoltage lockout level for longer than an internal UV turn-on delay of 160ms. Next, if VCCn is greater than 0.8V and ONn is low (<0.8V), a debounce delay of 10ms is started. If VCCn drops below 0.8V or ONn goes high before the end of the 10ms debounce delay, the debounce delay is restarted the next time these pins are properly conditioned. When the 10ms debounce delay expires, the external MOSFET is turned on by charging up the GATE with a 10A charge pump generated current source. When the GATE voltage reaches the MOSFET threshold voltage, the inrush current can build up quickly as the GATE continues to rise. The ACL amplifier actively controls the gate voltage to maintain 25mV across the sense resistor. In this condition, the inrush current is given by: 25mV IINRUSH = RSENSE As the inrush current charges up the load capacitor, the output rises with a corresponding increase in gate voltage. When the supply is no longer in current limit, an internal charge pump pulls the gate to 5.5V above the higher of VCC1 or VCC2 to achieve a low resistance power path. Figure 2 shows a typical start-up sequence with CLOAD1 = CLOAD2 = 150F RLOAD1 = 4.7 and RLOAD2 = 2. , The inrush current can be reduced to below the current limit level by adding an external gate capacitor as shown in Figure 3. GATE capacitor CGATE provides gate slew rate control to limit the inrush current. However, CGATE could cause parasitic high frequency self oscillation in Q1. A 10 resistor, RG, as shown in Figure 3 can be used to prevent the oscillation. To be effective, RG needs to be laid out close to Q1. The voltage at the GATE pin rises with a slope equal to IGATE / CGATE. For a given supply inrush current IINRUSH and load capacitor CLOAD, CGATE can be calculated according to: CGATE =
ON1/2 2V/DIV R1 0.015 VOUT1 5V/DIV VOUT2 5V/DIV 5V CLOAD VCC1 SENSE1 IGATE CGATE GATE1 GATE2 5V/DIV 5ms/DIV
422412 F02
IGATE IINRUSH
* CLOAD
Q1
RG 10
GATE1 5V/DIV
LTC4224
422412 F03
Figure 2. Normal Power-Up Sequence
Figure 3. Inrush Current Control by Gate Capacitor
422412fa
7
LTC4224-1/LTC4224-2 APPLICATIONS INFORMATION
If the voltage across the sense resistor R1 becomes too high, the inrush current is limited by the internal current limit circuitry. Turn-Off Sequence The MOSFETs can be turned off by the conditions summarized in Table 1.
Table 1. Turn-Off Conditions
CONDITION ON1 Goes High ON2 Goes High UVLO on VCC UVLO on VCC1 UVLO on VCC2 CH1 Overcurrent Fault CH2 Overcurrent Fault RESULT CHANNEL 1 CHANNEL 2 Turns Off No Effect Turns Off Turns Off No Effect Turns Off No Effect No Effect Turns Off Turns Off No Effect Turns Off No Effect Turns Off CLEARED BY ON1 Low ON2 Low VCC > UVLO VCC1 > UVLO VCC2 > UVLO ON1 High, UVLO on VCC1 ON2 High, UVLO on VCC2
0.2ms/DIV
422412 F04
ON1 2V/DIV VOUT1 5V/DIV
GATE1 5V/DIV
Figure 4. Normal Power-Down Sequence
When ON1 or ON2 is pulled high, the corresponding GATE pin is pulled to ground by 1.5mA. With the MOSFET off, the load current discharges the load capacitor. Figure 4 shows VCC1 supply turning off by pulling ON1 high with . RLOAD1 = 4.7 discharging CLOAD1 = 150F Overcurrent Fault The LTC4224 features an adjustable current limit with circuit breaker function that protects external MOSFETs against short circuits or excessive load current. The voltage across
the external sense resistor is monitored by the active current limit (ACL) amplifier and the electronic circuit breaker (ECB) comparator. An overcurrent condition results in the current being limited by the ACL amplifier. During current limiting, the ECB is activated and initiates a chain of logic and timing events to handle the fault. Figure 5 illustrates the LTC4224's response to an overcurrent condition on one supply output. Start-up and overcurrent control for the two supplies are independent. Before time point t1, the ON pin is high and the part is in reset. When the ON pin goes low, a 10ms debounce delay is started. After 10ms (time point t2), the external MOSFET is turned on by charging GATE with 10A. The load capacitor starts to charge up and the output voltage increases. At the same
ON
VOUT
IOUT FAULT
ILIMIT
ILIMIT
RESET t1
5ms START-UP 10ms DEBOUNCE DELAY BLANKING DELAY t2 t3
IDLE t4
OVERCURRENT 5ms ECB BLANKING DELAY 5ms ECB Arm t5 t6
422412 F05
Figure 5. Fault Handling Sequence
422412fa
8
LTC4224-1/LTC4224-2 APPLICATIONS INFORMATION
ON1 2V/DIV GATE1 5V/DIV
FAULT 5V/DIV
VOUT1 5V/DIV
IOUT1 1A/DIV GATE1 5V/DIV
IOUT1 1A/DIV
5ms/DIV
422412 F06
2ms/DIV
422412 F07
Figure 6. Start-Up with Short at Output
Figure 7. Overcurrent Fault on Output
time, a 5ms start-up blanking delay begins during which the circuit breaker is not allowed to latchoff the MOSFET. If the ECB is tripped at the end of 5ms (time point t3), the MOSFET is latched off by pulling GATE down with 1.5mA and FAULT is latched low. The waveform in Figure 6 shows an unsuccessful start-up due to a short circuit at the output. To ensure start-up, the load capacitor must be charged up sufficiently to exit current limit before the end of the 5ms blanking delay. For large load capacitors, it may be necessary to connect an external capacitor from GATE to GND as described in the Turn-On Sequence section. After start-up, any transient overcurrent faults lasting less than 100s are ignored. Any overcurrent condition lasting more than 100s will initiate the 5ms ECB blanking delay (time point t4). After the ECB blanking delay, the ECB is armed for the following 5ms (time point t5 to t6). Any 100s overcurrent pulse during this time latches off the MOSFET. In summary, for 5ms to 10ms after a 100s or greater overcurrent fault is detected, a second 100s fault condition causes the MOSFET to latchoff. If no overcurrent condition is detected during this time, the part re-enters the IDLE state and another blanking delay following an overcurrent condition is again required before the MOSFET latches off. Figure 7 shows how the output latches off following an overcurrent fault. During a severe short-circuit (see Figure 8), the output load current can briefly surge to tens of amperes. The LTC4224 rapidly brings the current under control by discharging
GATE2 5V/DIV
VOUT2 5V/DIV
IOUT2 8A/DIV
0.5s/DIV
422412 F08
Figure 8. Severe Short-Circuit on Output
the MOSFET's gate with 125mA towards ground. After a short delay, the ACL amplifier regulates the gate voltage until the ECB trips at the end of 5ms. Undervoltage Fault An undervoltage fault occurs if either VCC1 or VCC2 falls below 0.8V for longer than 8s. This turns off the affected supply's switch by discharging GATE with 1.5mA and clears its fault latch. An undervoltage fault on one supply does not affect the operation of the other supply. If VCC, the higher of VCC1 and VCC2, falls below 2.4V for more than 12s, all supply switches are turned off and all fault latches are cleared.
422412fa
9
LTC4224-1/LTC4224-2 APPLICATIONS INFORMATION
If there is significant supply lead inductance, a severe output short may collapse the input to ground before the LTC4224 can bring the current under control. In this case, the undervoltage lockout activates after an 8s filter delay, and the GATE is pulled down by 1.5mA. Resetting Faults Following an overcurrent fault, the LTC4224-1 latches off while the LTC4224-2 automatically restarts after a four second cool down period. An overcurrent fault on either supply causes the ECB for that supply to turn off the MOSFET and pull the FAULT pin low. Faults are reset by pulling the ON pin high for at least 20s, after which the FAULT pin releases and the turn-on sequence begins. Taking the lower supply below VCCLO(UVL) clears only that supply's fault and the turn-on sequence commences immediately. Pulling the higher supply below VCC(UVL) clears both supplies' faults and the turn-on sequence begins after a 160ms UV turn-on delay. When both supplies are above 2.5V, either supply going low only resets its own fault. For the auto-retry version (LTC4224-2), if the fault is not cleared within four seconds, the latched fault will be cleared automatically. FAULT will go high and the turn-on sequence will begin. A persistent fault results in an auto-retry duty cycle of about 0.1%. Figure 9 shows an auto-retry sequence as a result of an overcurrent fault. Gate Pin Voltage The gate drive is compatible with logic level MOSFETs, but caution is required if one supply is low. The guaranteed range of gate drive is 4.5V to 7V, with a typical value of 5.5V. Each GATE pin is clamped with respect to VCC, the higher of the two input supplies. When VCC is at 5V, both GATE pins can be as high as 12V above ground. If the lower supply is at 0V, the gate-to-source voltage of its MOSFET can be 12V. In such applications, MOSFETs with gate-to-source breakdown ratings of 12V or greater are recommended. Active Current Loop Compensation The active current loop is compensated by the parasitic capacitance of the external MOSFET. No further compensation components are normally required. In the case where a MOSFET with less than 600pF of gate capacitance is chosen, a 600pF compensation capacitor connected between the GATE pin and ground may be required. Supply Transient Protection In applications where the supply inputs are fed directly from the regulated output of the backplane supply, bulk bypassing assures a spike-free operating environment. In other applications where bulk bypassing is located far from the LTC4224, spikes generated during output shortcircuit events could exceed the absolute maximum ratings for VCC. To minimize such spikes, use wider traces or heavier trace plating to reduce the power trace inductance.
R2 0.010 VCC2 Q2 FDS6911
FAULT 5V/DIV VOUT CLOAD2
+
IOUT 1A/DIV Z1 SMAJ5.0A GATE 2V/DIV
VCC2 SENSE2 RSNUB 10 CSNUB 0.1F LTC4224 GND
GATE2
1s/DIV
422412 F10 422412 F09
Figure 9. Auto-Retry After Overcurrent Fault
Figure 10. Input Supply Transient Protection Network for Applications without Input Capacitance
422412fa
10
LTC4224-1/LTC4224-2 APPLICATIONS INFORMATION
VCC2 1 2 3 4 5 SENSE2 10 VCC2 9 GATE2 8 GND 7 LTC4224 6 VIAS TO GND PLANE
422412 F11
Z1
RSNUB CSNUB
SNUBBER NETWORK
PCB layout for the sense resistors and the power MOSFETs should include good thermal management techniques for optimal device power dissipation. A recommended PCB layout for the sense resistors and the power MOSFET around the LTC4224 is illustrated in Figure 12. Note that it is important to keep the trace from the LTC4224's GATE pin to the FDS6911's gate short. In Hot Swap applications where load currents can be 10A, wide PCB traces are recommended to minimize resistance and temperature rise. The suggested trace width for 1oz copper foil is 0.03" for each ampere of DC current to keep PCB trace resistance, voltage drop and temperature rise to a minimum. Note that the sheet resistance of 1oz copper foil is approximately 0.5m/square and voltage drops due to trace resistances add up quickly in high current applications. In most applications, it is necessary to use plated-through vias to make circuit connections from component layers to power and ground layers internal to the PCB. For 1oz copper foil plating, a general rule is 1A of DC current per via. Consult your PCB fabrication facility for design rules pertaining to other plating thicknesses. Design Example As a design example, consider the following specifications: VCC1 = 5V, VCC2 = 3.3V, ILOAD1(MAX) = 1A, ILOAD2(MAX) = 2A, CLOAD1 = CLOAD2 = 150F (see Figure 1). First, select the sense resistor for each supply. Calculate the R1 and R2 values based on the maximum load current and the minimum circuit breaker threshold limit, VSENSE(CB)(MIN). If a 1% tolerance is assumed for the sense resistors, then the following values of resistance should suffice:
Table 2. Sense Resistor Values
SUPPLY VOLTAGE 5V 3.3V RSENSE (1%) 15m 10m ITRIP(MIN) 1.49A 2.23A ITRIP(MAX) 1.85A 2.78A
Figure 11. Recommended Layout for Input Supply Transient Protection Network
Also, bypass locally with a 10F electrolytic and 100nF ceramic, or alternatively clamp the input with a transient voltage suppressor (Z1) as shown in Figure 10. A 10, 100nF snubber damps the response and eliminates ringing. A recommended layout of the transient protection devices Z1, RSNUB and CSNUB around the LTC4224 is shown in Figure 11. PCB Layout Considerations For proper operation of the LTC4224's electronic circuit breaker, Kelvin connections to the sense resistors are strongly recommended. The PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the
3.3V R2
5V R1 8 5 6 7
10 9 8 7 6 LTC4224 11
1 2 3 4 5 1
FDS6911
2
3
4
BOTTOM SIDE
TOP SIDE
422412 F12
Figure 12. Recommended Layout for Power MOSFET and Sense Resistors
For proper operation, ITRIP(MIN) must exceed the maximum load current with margin, so RSENSE1 = 15m and RSENSE2 = 10m should suffice for the VCC1 and VCC2 supplies respectively.
422412fa
11
LTC4224-1/LTC4224-2 APPLICATIONS INFORMATION
Next, assume that there is no load current at start-up, and calculate the inrush current required to charge the load capacitor. As there is no gate capacitor, the supplies start-up in current limit. Compute the time, tSU, it takes to fully charge the load capacitor: t SU = VCC * CLOAD ITRIP The worst-case PAVG is calculated to be 4.6W for both the 5V supply and the 3.3V supply. In this example, the FDS6911 MOSFET offers a good solution. Since this MOSFET is a dual N-channel in a single SO8 package, it must be able to tolerate the combined power dissipation of both supplies during the tSU start-up time. The increase in steady-state junction temperature due to power dissipated in the MOSFET is T = PAVG*ZTH where ZTH is the thermal impedance. Under this condition, the FDS6911 datasheet's Transient Thermal Impedance plot indicates that the junction temperature will increase by 6.4C using ZTHJC = 0.7C/W (single pulse). The FDS6911's on-resistance is 17m at VGS = 4.5V, 25C. The magnitude of the power pulse that results during a severe overload is calculated to be 9.25W for the 5V supply and 9.2W for the 3.3V supply under the worst case conditions. Assuming a worst-case circuit breaker timeout period of 7.5ms, the junction temperature will increase by 25C, with one supply short-circuited. If both supplies are short-circuited, the junction temperature will increase by 50C in the worst-case. During auto-retry (LTC4224-2), in the event of persistent faults at both supplies, the ample four second cooling delay limits the increase in junction temperature to 50C. The SOA curves of the FDS6911 indicate that the above conditions are safe.
Table 3 lists the worst-case tSU values assuming 30% tolerance for load capacitances.
Table 3. Worst-Case tSU
VOLTAGE SUPPLY 5V 3.3V tSU(MIN) 0.53ms 0.23ms tSU(MAX) 0.65ms 0.29ms
The start-up ECB blanking delay is guaranteed to be at least 2.5ms, which is longer than the tSU tabulated in Table 3. Hence, both supplies can start up successfully. Next, verify that the thermal ratings of the selected external MOSFETs are not exceeded during power-up or an output short-circuit. Assuming the MOSFET dissipates power only due to inrush current charging the load capacitor, the energy dissipated in the MOSFET during power-up is the same as that stored in the load capacitor after power-up. The average power dissipated in the MOSFET is given by: PAVG = CLOAD * VOUT 2 2 * t SU
422412fa
12
LTC4224-1/LTC4224-2 TYPICAL APPLICATION
5V and 3.3V Card Resident Application
R1 0.004 5V Z1 RSNUB1 10 CSNUB1 100nF Q1 Si7336ADP
5V 5A
3.3V Z2 RSNUB2 10 CSNUB2 100nF R3 10k
R2 0.004
Q2 Si7336ADP
3.3V 5A
VCC1 FAULT ON1 ON2
SENSE1
VCC2
SENSE2
GATE1
GATE2
PWRFLT PWREN
LTC4224
GND
GND
BACKPLANE CONNECTOR
CARD CONNECTOR
Z1: SMAJ6.5A Z2: SMAJ5.0A
422412 TA02
Hot Swap Application for Two Add-In Cards
R1 0.004 5V PRSNT1 Q1 Si7336ADP
5V 5A
R3 10k
VCC1 FAULT
SENSE1
GATE1 ON1 BACKPLANE CONNECTOR1 BACKPLANE CONNECTOR2 CARD CONNECTOR1 CARD CONNECTOR2
LTC4224 GND VCC2 SENSE2 ON2 GATE2
PRSNT2 R2 0.004 Q2 Si7336ADP 5V 5A
422412 TA03
422412fa
13
LTC4224-1/LTC4224-2 PACKAGE DESCRIPTION
DDB Package 10-Lead Plastic DFN (3mm x 2mm)
(Reference LTC DWG # 05-08-1722)
0.64 0.05 (2 SIDES) 0.70 0.05 2.55 0.05 1.15 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.39 0.05 (2 SIDES) PIN 1 BAR TOP MARK (SEE NOTE 6) 0.200 REF
3.00 0.10 (2 SIDES)
R = 0.05 TYP 2.00 0.10 (2 SIDES)
R = 0.115 TYP 6
0.40 0.10 10
0.75 0.05
0.64 0.05 (2 SIDES) 5 0.25 0.05 2.39 0.05 (2 SIDES)
1
PIN 1 R = 0.20 OR 0.25 x 45 CHAMFER
(DDB10) DFN 0905 REV O
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0 - 0.05
BOTTOM VIEW--EXPOSED PAD
422412fa
14
LTC4224-1/LTC4224-2 PACKAGE DESCRIPTION
MS Package 10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 0.127 (.035 .005)
5.23 (.206) MIN
3.20 - 3.45 (.126 - .136) 3.00 0.102 (.118 .004) (NOTE 3)
0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT
10 9 8 7 6
0.497 0.076 (.0196 .003) REF
0.254 (.010) GAUGE PLANE
DETAIL "A" 0 - 6 TYP
4.90 0.152 (.193 .006)
3.00 0.102 (.118 .004) (NOTE 4)
12345 0.53 0.152 (.021 .006) DETAIL "A" 0.18 (.007) SEATING PLANE 0.17 -0.27 (.007 - .011) TYP 0.1016 0.0508 (.004 .002)
MSOP (MS) 0307 REV E
1.10 (.043) MAX
0.86 (.034) REF
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.50 (.0197) BSC
422412fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC4224-1/LTC4224-2 TYPICAL APPLICATION
X2/XENPAK Hot Swap Application
R1 0.010 APS BULK SUPPLY BYPASS CAPACITOR 3.3V BULK SUPPLY BYPASS CAPACITOR Q2 R3 390 VCC1 SENSE1 VCC2 SENSE2 GATE1 GATE2 ON1 LTC4224 FAULT ON2 GND 1k GND Q1 R2 0.010 FDS6911 APS 2A
3.3V 2A
D1
APS: 1V TO 1.8V
CONNECTOR
PLUG-IN CARD
422412 TA04
RELATED PARTS
PART NUMBER LTC1421 LTC1645 LTC1647 LTC4210 LTC4211 LTC4212 LTC4213 LTC4215 LTC4216 LTC4218 LTC4221 LTC4223 DESCRIPTION Two Channel Hot Swap Controller Dual Channel Hot Swap Controller Dual Channel Hot Swap Controller Single Channel Hot Swap Controller Single Channel Hot Swap Controller Single Channel How Swap Controller Electronic Circuit Breaker Single Channel Hot Swap Controller Single Channel Hot Swap Single Channel Hot Swap Controller Dual Channel Hot Swap Controller Dual Supply Hot Swap Controller COMMENTS Operates from 3V to 12V and Supports -12V Operates from 3V to 12V, Power Sequencing Operates from 2.7V to 16.5V, Separate ON Pins to Sequence Operates from 2.7V to 16.5V, Active Current Limiting 2.5V to 16.5V, Multifunction Current Control 2.5V to 16.5V, Multifunction Current Control with Power Good Input Operates from 2.3V to 6V, No RSENSETM Electronic Circuit Breaker Operates from 2.9V to 15V, I2C Compatible Monitoring Operates from 0V to 6V Operates from 2.9V to 26.5V, Adjustable, 5% Accurate (15mV) Current Limit Operates from 1V to 13.5V, Multifunction Current Control Controls 12V and 3.3V for AMC and TCA
422412fa
16 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 1108 REV A * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2008

▲Up To Search▲

Price & Availability of LTC4224IMS-1-PBF

	To Download LTC4224IMS-1-PBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .